• DocumentCode
    3513076
  • Title

    A new hardware implementation of the H.264 8×8 transform and quantization

  • Author

    Park, Jeoong Sung ; Ogunfunmi, Tokunbo

  • Author_Institution
    Dept. of Comput. Eng., Santa Clara Univ., Santa Clara, CA
  • fYear
    2009
  • fDate
    19-24 April 2009
  • Firstpage
    585
  • Lastpage
    588
  • Abstract
    H.264/AVC is the most powerful technology in video compression/transmission area because of its high coding efficiency and robustness. In this paper, we propose a new hardware architecture of 8times8 integer transform and quantization for H.264 which promises very low resource utilization. In the architecture, each pixel is processed one by one on a simplified pipeline without multiplication. Thus, redundant modules, which are used for block-based or row-based parallel processing, can be reduced. Experimental results show that it can reduce resource usage 30% compared to previously proposed models. It can be used for mobile applications. It covers a wide range of parameters as well.
  • Keywords
    data compression; matrix algebra; quantisation (signal); transforms; video coding; H.264/AVC; hardware architecture; integer transform; quantization; row-based parallel processing; video compression; video transmission; Automatic voltage control; Bit rate; Hardware; Parallel processing; Quantization; Real time systems; Robustness; Transforms; Video coding; Video compression; H.264; integer transform; quantization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech and Signal Processing, 2009. ICASSP 2009. IEEE International Conference on
  • Conference_Location
    Taipei
  • ISSN
    1520-6149
  • Print_ISBN
    978-1-4244-2353-8
  • Electronic_ISBN
    1520-6149
  • Type

    conf

  • DOI
    10.1109/ICASSP.2009.4959651
  • Filename
    4959651