DocumentCode :
3513302
Title :
Modeling Verification, Validation, and Uncertainty Quantification (VV&UQ) procedure for a two-level three-phase boost rectifier
Author :
Ahmed, Sara ; Burgos, R. ; Roy, Chris ; Boroyevich, D. ; Mattavelli, Paolo ; Wang, F.
Author_Institution :
Center for Power Electron. Syst. (CPES), Virginia Tech, Blacksburg, VA, USA
fYear :
2012
fDate :
5-9 Feb. 2012
Firstpage :
1894
Lastpage :
1901
Abstract :
This paper presents complete Verification, Validation, and Uncertainty Quantification (VV&UQ) procedures that are applied to a two-level boost rectifier. The goal of this VV&UQ study is the improvement of the modeling procedure for power electronics systems, and the full assessment of the boost rectifier model (as an example) predictive capabilities. Modeling and simulation of large systems is always the preferred solution to avoid repetitive hardware, and to minimize the cost. However, developing the accurate models and making sure it matches the hardware is always a challenge. This paper provides a set of procedures that if followed one can claim the model is validated.
Keywords :
rectifiers; rectifying circuits; VV&UQ procedure; cost minimization; power electronics systems; repetitive hardware avoidance; two-level three-phase boost rectifier; verification, validation, and uncertainty quantification procedure modeling; Current measurement; Power measurement; Predictive models; Rectifiers; Semiconductor device measurement; Uncertainty; Voltage measurement; Two level boost rectifier; verification and validation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4577-1215-9
Electronic_ISBN :
978-1-4577-1214-2
Type :
conf
DOI :
10.1109/APEC.2012.6166081
Filename :
6166081
Link To Document :
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