DocumentCode :
351352
Title :
Achieving the quality of verification for behavioral models with minimum effort
Author :
Chen, Tom ; Von Mayrhauser, Anneliese ; Sahinoglu, Mehmet ; Hajjar, Amjad ; Anderson, Charles
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
fYear :
2000
fDate :
2000
Firstpage :
234
Lastpage :
239
Abstract :
When designing a system in the behavioral level, one of the most important steps to be taken is verifying its functionality before it is released to the logic/PD design phase. One may consider behavioral models as oracles in industries to test against when the final chip is produced. In this work, we use branch coverage as a measure for the quality of verifying/testing behavioral models. Minimum effort for achieving a given quality level can be realized by using the proposed stopping rule. The stopping rule guides the process to switch to a different testing strategy using different types of patterns, i.e. random vs. functional, or using different set of parameters to generate patterns/test cases, when the current strategy is expected not to increase the coverage. We demonstrate the use of the stopping rule on two complex behavioral level VHDL models that were tested for branch coverage with 4 different testing phases. We compare savings of the number of applied testing patterns and quality of testing both with and without using the stopping rule, and show that switching phases at certain points guided by the stopping rule would yield to the same or even better coverage with less number of testing patterns
Keywords :
Bayes methods; formal verification; hardware description languages; integrated circuit design; logic CAD; Bayesian estimator; Bayesian stopping rule; VHDL models; behavioral models; branch coverage; chip design; testing patterns; testing quality; testing strategy; verification quality; Bayesian methods; Computer bugs; Computer science; Distributed computing; Information analysis; Information science; Logic design; Semiconductor device measurement; Software testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0525-2
Type :
conf
DOI :
10.1109/ISQED.2000.838877
Filename :
838877
Link To Document :
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