Correct-by-design CAD enhancement for EMI and signal integrity

The monolithic integration of mixed-signal and RF microelectronics is straining the capabilities of present CAD roots for predictive analysis. In particular, the effects of di/dt, crosstalk, high-frequency impedance matching, and substrate noise pose challenges to reliable circuit operation. This is especially true as supply rail voltages continue to shrink below 2.5 V. Although PCB CAD tools have successfully addressed these issues, similar. tools have yet to penetrate the VLSIC/RFIC market due to the even greater signal frequencies and far greater network density. We describe an ongoing research effort to introduce models of these effects into a commercial CAD tool. The goal is to develop a correct-by-design CAD system in which constraints on signal crosstalk and EMI are considered along with signal delay and power restrictions in performing automated floor-planning and routing. To permit top-down synthesis of reliable systems, we are also expanding the HDL coding of digital systems to include two additional parameters: EMI victim status and EMl point-source contributions