DocumentCode
3513848
Title
A comparison of two multistage ring architectures for NoC using high-level simulation models
Author
Bourduas, S. ; Zilic, Z.
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC
fYear
2008
fDate
15-15 Oct. 2008
Firstpage
37
Lastpage
40
Abstract
This paper uses high-level simulation models written in SystemC to compare the performance characteristics of two wormhole-routed multistage ring architectures: a hierarchical ring and a two-dimensional hyper ring. The hierarchical ring architecture has a single global ring, which limits its bisection bandwidth. The hyper ring is presented as an improvement over the hierarchical ring, whereby a second global ring is used to double the bisection bandwidth. Furthermore, a ldquofatrdquo variant of each architecture is considered, which use bidirectional global rings to increase the bisection bandwidth of the original architectures.
Keywords
multistage interconnection networks; network-on-chip; bidirectional global rings; bisection bandwidth; high-level simulation models; network-on-chip; two-dimensional hyper ring; wormhole-routed multistage ring architectures; Bandwidth; Computational modeling; Computer architecture; Computer simulation; Design methodology; Network topology; Network-on-a-chip; Software testing; System-on-a-chip; Writing; ESL; NoC; modeling; ring; simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Microsystems and Nanoelectronics Research Conference, 2008. MNRC 2008. 1st
Conference_Location
Ottawa, Ont.
Print_ISBN
978-1-4244-2920-2
Electronic_ISBN
978-1-4244-2921-9
Type
conf
DOI
10.1109/MNRC.2008.4683372
Filename
4683372
Link To Document