Traffic scheduling coprocessor with schedulability analysis capability

The low processing power of typical fieldbus nodes used in real-time applications usually limits the sort of message scheduling that can be done, and precludes any kind of on-line schedulability analysis. Moving these computationally intensive tasks to dedicated hardware is an effective way to remove this limitation and achieve the best temporal determinism. This paper presents a traffic scheduling and schedulability analyser coprocessor targeted for centralised scheduling fieldbus systems. The FPGA-based coprocessor generates message schedules according to one of three different scheduling policies, and allows the number of message and their respective parameters to be change dynamically. The schedulability analyser capability supports on-line admission control of new messages. The paper starts by discussing the basic feature which such a coprocessor should include. Then the coprocessor architecture is described together with several relevant implementation details. Finally the worst case execution times of its two main functions are derived, validating the coprocessor´s feasibility