Level assignment for displaying combinational logic

Netlist viewers in VLSI CAD usually display gate-level circuits in a column-oriented style for easy readability. Each gate has to be assigned to one column, called a “level” in the following. In this paper we present a level assignment algorithm that finds application in displaying large netlists. The algorithm has polynomial worst case behavior and in contrast to standard depth first search (DFS) methods computes well balanced graphs resulting in improved graphics. A large set of experiments is given to point out the differences between DFS and the new interval algorithm