• DocumentCode
    3514567
  • Title

    SiP and WLP-CSP Trends: State-of-the-art and future trends

  • Author

    Yannou, Jean-Marc

  • Author_Institution
    NXP Semicond., Caen
  • fYear
    2008
  • fDate
    1-4 Sept. 2008
  • Firstpage
    3
  • Lastpage
    6
  • Abstract
    Wafer-Level Chip-Scale-Packaging (WLCSP) and System-in-Package (SiP) integration recently confirmed themselves as two long lasting increasing trends of the semiconductor industry. Even though they are driven by the same motivations of miniaturization and performance enhancement, they still follow parallel tracks, and rarely mix with one another in products. However, there is evidence that once reliability as well as some cost issues will be overcome thanks to innovation, future products will benefit from their combined differentiated advantages. We will present the state-of-the-art of both WLCSP and SiP, and we will then make clear under which conditions both these trend can be combined with cumulative benefits. We will then show new innovation trends aiming at fulfilling these conditions. Last, a few applications combining the benefits of WLCSP and SiP will be listed.
  • Keywords
    chip scale packaging; system-in-package; SiP; WLP-CSP; semiconductor industry; system-in-package; wafer-level chip-scale-packaging; Assembly; Chip scale packaging; Costs; Electronics industry; Electronics packaging; Integrated circuit interconnections; Integrated circuit packaging; Receivers; Technological innovation; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd
  • Conference_Location
    Greenwich
  • Print_ISBN
    978-1-4244-2813-7
  • Electronic_ISBN
    978-1-4244-2814-4
  • Type

    conf

  • DOI
    10.1109/ESTC.2008.4684312
  • Filename
    4684312