DocumentCode :
351459
Title :
Static timing analysis taking crosstalk into account
Author :
Ringe, Matthias ; Lindenkreuz, Thomas ; Barke, Erich
Author_Institution :
IBM Deutschland GmbH, Boeblingen, Germany
fYear :
2000
fDate :
2000
Firstpage :
451
Lastpage :
455
Abstract :
Capacitance coupling can have a significant impact on gate delay in today´s deep submicron circuits. In this paper we present a static timing analysis tool that calculates the longest path of synchronous circuits taking the impact of crosstalk on gate delays into account. We show that passive modeling of the coupling capacitance can significantly underestimate the delay and that an assumption of permanent worst-case coupling unnecessarily overestimates it. Our method is validated by comparison to Spice simulations
Keywords :
VLSI; capacitance; circuit analysis computing; crosstalk; delay estimation; digital integrated circuits; iterative methods; timing; capacitance coupling; coupling delay model; crosstalk; deep submicron circuits; gate delay model; gate delays; static timing analysis tool; synchronous circuits; Capacitance; Contracts; Couplings; Crosstalk; Delay; MOSFETs; Microelectronics; Threshold voltage; Timing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
Type :
conf
DOI :
10.1109/DATE.2000.840310
Filename :
840310
Link To Document :
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