An integrated reset / pulse pile-up rejection circuit for pixel readout ASIC´s

Author

Bastia, P. ; Bertuccio, G. ; Borghetti, F. ; Caccia, S. ; Ferragina, V. ; Ferrari, F. ; Maiocchi, D. ; Malcovati, P. ; Martin, D. ; Pullia, A. ; Ratti, N.

Author_Institution

Alenia Spazio S.p.A., Vimodrone, Italy

Volume

3

fYear

2004

fDate

16-22 Oct. 2004

Firstpage

1415

Abstract

We present a compact and low power integrated circuit designed to control the reset and performs the pulse pile-up rejection in multi-channel spectroscopic-grade ASIC´s. The circuit has been implemented in 0.35 mum CMOS technology with an area of 60times80 mum² and null static power consumption. These features makes this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X and gamma ray pixel detectors.

Keywords

CMOS integrated circuits; X-ray detection; X-ray imaging; X-ray spectrometers; application specific integrated circuits; gamma-ray detection; gamma-ray spectrometers; nuclear electronics; position sensitive particle detectors; readout electronics; 0.35 mum; CMOS technology; X-ray imaging detectors; compact integrated circuit; front-end readout cells; gamma-ray imaging detectors; integrated reset-pulse pile-up rejection circuit; low power integrated circuit; multichannel spectroscopic-grade ASIC; null static power consumption; pixel detectors; pixel readout ASIC; spectroscopic detectors; CMOS technology; Energy consumption; Gamma ray detection; Gamma ray detectors; Integrated circuit technology; Optical imaging; Pixel; Power integrated circuits; Pulse circuits; Spectroscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium Conference Record, 2004 IEEE

Conference_Location

Rome

ISSN

1082-3654

Print_ISBN

0-7803-8700-7

Electronic_ISBN

1082-3654

Type

conf

DOI

10.1109/NSSMIC.2004.1462505

Filename

1462505