Implementing decision trees in hardware

In this paper several hardware implementations of decision trees (axis-parallel, oblique and non-linear) based on the concept of universal node and sequence of universal nodes are presented. Proposed hardware architectures are suitable for the implementation in both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Proposed architectures can be easily customized in order to fit a wide variety of application requirements, fulfilling their role as general purpose building blocks for System on Chip designs. Experimental results obtained on 23 datasets of standard University of California Irvine (UCI) Machine Learning Repository database suggest that the proposed architecture based on the sequence of universal nodes requires on average 56% less hardware resources compared with the previously proposed architectures, having the same throughput.