Characterization of MOS transistors after TSV fabrication and 3D-assembly

Room-temperature bonding by means of mechanical caulking to electrically interconnect stacked chips using through-silicon vias can greatly reduce process cost. We have already demonstrated the feasibility of this approach in several test samples. However, in a three-dimensional system-in-package sample containing a commercially available microcomputer unit, we encountered some difficulties in manufacturing TSVs in a high-yield ratio. To overcome these difficulties and thereby achieve high-yield TSV fabrication in our process, we devised a new electrode structure. By connecting the TSVs to internal copper lands formed at the back-end metal layers, we achieved a high-yield TSV fabrication of more than 99 %. To evaluate the impact of the TSV processing and proximity on MOS transistor performance, we measured the drain saturation current (I_DSAT) in MOS transistors. The MOS transistors operated successfully without any degradation of performance in both the post-processing of TSVs and the post-assembly by mechanical caulking at room temperature.