• DocumentCode
    3514987
  • Title

    On the optimization power of redundancy addition and removal for sequential logic optimization

  • Author

    Millán, Enrique San ; Entrena, Luis ; Espejo, José Alberto

  • Author_Institution
    Electr., Electron. & Autom. Eng. Dept., Univ. Carlos III, Madrid, Spain
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    292
  • Lastpage
    299
  • Abstract
    The paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques
  • Keywords
    circuit optimisation; redundancy; sequential circuits; logic transformations; optimization power; redundancy addition and removal; retiming and resynthesis techniques; sequential circuits; sequential logic optimization; Automation; Equivalent circuits; Flip-flops; Logic gates; Optimization methods; Power engineering and energy; Redundancy; Sequential circuits; Testing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Systems Design, 2001. Proceedings. Euromicro Symposium on
  • Conference_Location
    Warsaw
  • Print_ISBN
    0-7695-1239-9
  • Type

    conf

  • DOI
    10.1109/DSD.2001.952305
  • Filename
    952305