Thermal impact of randomly distributed solder voids on Rth-JC of MOSFETs

The work presented applies a statistical approach to study randomly distributed solder voids in MOSFET products. The grid size was varied as independent of the mesh element to account for typical void sizes observed in X-ray images. Thereafter the impact of random voids for different chip sizes was quantified. Results show that higher maximum chip temperatures can occur with voids located in the corner of the die. A simple analytical expression thereafter was developed to understand and explain this. Rth-JC (thermal resistance junction-to-case) and IR (infrared) measurements of selected test devices with known void distribution were performed as well. Measurement and simulated results were compared. In this work we attempt to establish a model for the evaluation of the process impact on Rth-JC. It also leads to some guidelines of solder joint inspection criteria for power devices.