Wire bonding power interconnection

This paper describes recent developments in the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realized. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasized. The aim of this paper is to improve the reliability of semiconductor chip power interconnection and to increase the durability of these structures. The first objective is to determine stress distribution in connection wires. Wire cracks may occur in places of maximal stress. Another objective is to investigate current distribution in wires. The theoretical results will be completed with data from real experiments.