Title :
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Author :
Yang, Chengmo ; Orailoglu, Alex
Author_Institution :
Comput. Sci. & Eng. Dept., Univ. of California, La Jolla, CA, USA
fDate :
June 29 2009-July 2 2009
Abstract :
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliability. Temperature hotspots not only accelerate the physical failure mechanisms such as electromigration and dielectric breakdown, but furthermore make the system more vulnerable to timing-related intermittent failures. Traditional thermal management techniques suffer from considerable performance overhead as the entire processor needs to be stalled or slowed down to preclude heat accumulation. Given the significant temporal and spatial variations of the chip-wide temperature, we propose in this paper a technique that directly targets one of the resources that is most likely to overheat in current processors, namely, the register files. Instead of duplicating or physically distributing the register file, we suggest to attain power density control through exploiting the extant spatial slack associated with register file accesses. Based on application-specific access profiles, a compiler-directed register shuffling strategy is proposed to deterministically construct the logical to physical register mapping in a rotating manner. Simulation results confirm that the proposed technique attains, within a limited hardware budget and negligible performance degradation, effective reduction in peak temperature and hence in the expected fault rates for the entire chip.
Keywords :
circuit reliability; microprocessor chips; optimising compilers; power control; application-specific access profiles; chip-wide temperature; compiler-directed register file peak temperature reduction; compiler-directed register shuffling strategy; dielectric breakdown; electromigration; imminent processor architecture heat wall; physical failure mechanism; physical register mapping; power density control; processor reliability enhancement; semiconductor technology generation; simulation result; thermal management technique; Acceleration; Dielectric breakdown; Electromigration; Failure analysis; Hardware; Registers; Semiconductor device reliability; System performance; Temperature; Thermal management;
Conference_Titel :
Dependable Systems & Networks, 2009. DSN '09. IEEE/IFIP International Conference on
Conference_Location :
Lisbon
Print_ISBN :
978-1-4244-4422-9
Electronic_ISBN :
978-1-4244-4421-2
DOI :
10.1109/DSN.2009.5270305