Title :
Effect of interface states (Dit) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells
Author :
Alnuaimi, Aaesha ; Nayfeh, Ammar
Author_Institution :
Masdar Inst. of Sci. & Technol. Microsyst. Eng., Abu Dhabi, United Arab Emirates
Abstract :
The effect of interface states (Dit) at the a-Si/c-Si interface on the performance of a-Si(n+)/c-Si(p)/c-Si(p+) heterojunction solar cells is investigated using Physics Based TCAD simulation. Dit is simulated as Gaussian distribution with peak ranging from 1×109 cm-2 to 1×1015 cm-2. In addition, c-Si layers of 4, 3, 2, 1, and 0.5 μm are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2μm c-Si layer with 100μs lifetime, the results show a drop in open-circuit voltage (Voc) from 0.68 V to 0.52 V as Dit increases from 1×109 cm-2 to 1×1015 cm-2. The efficiency drops from 8% to 6%. The short-circuit current (Jsc) does not change with Dit and is only a function of thickness and lifetime.
Keywords :
Gaussian distribution; amorphous semiconductors; elemental semiconductors; interface states; semiconductor heterojunctions; semiconductor thin films; short-circuit currents; silicon; solar cells; technology CAD (electronics); Gaussian distribution; Si-Si-Si; a-Si-c-Si Interface; c-Si layer lifetime; interface state effect; open-circuit voltage; physics based TCAD simulation; short-circuit current; size 0.5 mum to 4 mum; thin film heterojunction solar cell performance; Electron traps; Heterojunctions; Interface states; Photovoltaic cells; Physics; Silicon; Interface States; Lifetime; Photovoltaic Cells; Silicon;
Conference_Titel :
Photovoltaic Specialists Conference (PVSC), 2012 38th IEEE
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-0064-3
DOI :
10.1109/PVSC.2012.6317770
