DocumentCode
3516206
Title
A Serial Logarithmic Number System ALU
Author
Arnold, Mark G. ; Vouzis, Panagiotis D.
Author_Institution
Lehigh Univ., Bethlehem, PA, USA
fYear
2007
fDate
29-31 Aug. 2007
Firstpage
151
Lastpage
156
Abstract
Serial arithmetic uses less hardware than parallel arithmetic. Serial floating point (FP) is slower than parallel FP. The Logarithmic Number System (LNS) simplifies operations, but a fast serial implementation of LNS has never been proposed previously. This paper presents a fast bit-serial LNS that combines a novel serial implementation of Mitchell´s method and a new error correction method that is compatible with least-significant-bit-first serial arithmetic.
Keywords
error correction; finite state machines; logic circuits; microprocessor chips; pipeline arithmetic; ALU; Mitchell´s method; error correction method; fast bit-serial LNS; least-significant-bit-first serial arithmetic; pipelined fashion; serial logarithmic number system; state machines; timing information; Arithmetic; Circuits; Clocks; Concurrent computing; Design methodology; Digital systems; Error correction; Hardware; Logic; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location
Lubeck
Print_ISBN
978-0-7695-2978-3
Type
conf
DOI
10.1109/DSD.2007.4341463
Filename
4341463
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