Title :
Area-efficient layout design for output transistors with consideration of ESD reliability
Author :
Ker, Ming-Dou ; Wu, Chuns-Yu ; Huang, Chien-Chang ; Chang, Hun-Hsien ; Wu, Chau-Neng ; Yu, Ta-Lee
Author_Institution :
Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A novel hexagon-type layout is proposed to realize large-dimension CMOS output transistors with smaller layout area but higher ESD reliability. The drain parasitic capacitance of hexagon-type layout is also smaller than that of traditional finger-type layout. Experimental results have shown that the maximum driving capability per layout area of output transistor with hexagon-type layout is improved 30% more than that with finger-type layout. This hexagon-type layout is very suitable for deep-submicron low-voltage CMOS ICs in high-density applications
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; integrated circuit layout; semiconductor device reliability; CMOS output transistor; ESD reliability; area efficiency; deep-submicron low-voltage CMOS IC; hexagon-type layout; layout design; parasitic capacitance; CMOS technology; Circuits; Electrostatic discharge; Fingers; Industrial electronics; Laboratories; MOS devices; Protection; Robustness; Transistors;
Conference_Titel :
Electron Devices Meeting, 1996., IEEE Hong Kong
Print_ISBN :
0-7803-3091-9
DOI :
10.1109/HKEDM.1996.566324
