Chip-package interactions: Some combined package effects on copper/low-k interconnect delaminations

The introduction of brittle dielectric materials, and the feature size decrease of IC chips to follow Moorepsilas law, are well known to pose great integration challenges. In this paper, a 3D fully parameterized Finite Elements of a Ball Grid Array package model is built and thermo-mechanical stress produced during package operations is evaluated. That aims to address FE-BE compatibility concerns. Thanks to multi level and energy based post processing methods, both analysis at the package and interconnect levels are carried out. The preliminary analysis at the package displacements and comparison with measurement maps allow to validade the package model. Localized evaluation of the crack propagation likelihood into the low-k stack underlines the particular effects of the glue fillet geometry and die attach thickness. On the other hand a drastic rise of the fracture risk is suspected with highest values of the glue fillet, and for the considered configurations, with thinest die attach. The sensitivity to shear modes, contrary to compressive one is highlighted, and released energy plots indicate an higher delamination hazard in the bottommost IMD layers. Possible extended applications of this work are the early phases of technology developments and product crisis solving.