DocumentCode
3516602
Title
Performance evaluation of lot dispatching and scheduling algorithms through discrete event simulation
Author
O´Neil, Pat
Author_Institution
Motorola, Tempe, AZ, USA
fYear
1991
fDate
20-22 May 1991
Firstpage
21
Lastpage
24
Abstract
The effect of wafer factory production rules on factory capacity, WIP (work in process), and cycle time is investigated. Algorithms involving lot start rules, equipment loading rules, and lot priority assignment rules are evaluated. Specific rules are found optimum for the factory analyzed here. The spread between worst-case and best-case operating rules is quantified. More importantly, during the course of the investigation it became apparent that reliable methods of rule enforcement and verification are vital, because the tendency is for the undisciplined factory to settle toward worst-case, operating rules
Keywords
discrete event simulation; dispatching; integrated circuit manufacture; manufacturing data processing; production control; scheduling; cycle time; discrete event simulation; equipment loading rules; factory capacity; lot dispatching; lot priority assignment rules; lot start rules; operating rules; performance evaluation; rule enforcement; rule verification; scheduling algorithms; wafer factory production rules; work in process; Analytical models; Discrete event simulation; Dispatching; Equipment failure; Failure analysis; Job shop scheduling; Production facilities; Scheduling algorithm; Semiconductor device manufacture; Semiconductor device packaging;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Science Symposium, 1991. ISMSS 1991., IEEE/SEMI International
Conference_Location
Burlingame, CA
Print_ISBN
0-7803-0027-0
Type
conf
DOI
10.1109/ISMSS.1991.146260
Filename
146260
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