On-Chip Verification of NoCs Using Assertion Processors

NoC verification has become an increasingly difficult task due to the growing complexity of these systems. In this paper, we propose a methodology based on assertions for on-chip verification of NoCs. We have a local assertion processor (LAP) in each core to manage the outputs of assertions inside it. To route assertions´ outputs toward this processor, we offer a boundary scan chain mechanism. Moreover, after detecting error, each LAP dispatches a packet called error packet to a global assertion processor (GAP) which receives error packets from all cores and performs necessary actions regarding to errors and their severities. Finally, in order to evaluate our method, we apply it on an NoC structure and show the experimental results.