DocumentCode
3517225
Title
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties
Author
Skarvada, Jaroslav ; Herrman, Tomas ; Kotasek, Zdenek
Author_Institution
Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic
fYear
2007
fDate
29-31 Aug. 2007
Firstpage
611
Lastpage
618
Abstract
In the paper, the methodology of testability analysis based on the concept of testable blocks is presented. In the methodology the power consumption during test application is also taken into account. For this purpose, power estimation tool was developed and implemented. Integration of the developed software into the professional design flow is described. Experimental results gained as a consequence of applying the methodology on both benchmark and practical designs are demonstrated. The intensions for future research are presented.
Keywords
design for testability; logic design; logic testing; RTL; power consumption; power estimation tool; professional design flow; testability analysis; testable blocks identification; Application software; CMOS technology; Circuit testing; Design methodology; Energy consumption; Information analysis; Information technology; Paper technology; Power dissipation; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
Conference_Location
Lubeck
Print_ISBN
978-0-7695-2978-3
Type
conf
DOI
10.1109/DSD.2007.4341531
Filename
4341531
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