Title :
Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application
Author :
Sun, Y. ; Yu, H.Y. ; Singh, N. ; Gnani, E. ; Baccarani, G. ; Leong, K.C. ; Lo, G.Q. ; Kwong, D.L.
Author_Institution :
Inst. of Microelectron., A*STAR, Singapore, Singapore
Abstract :
This study presents vertical Si-nanowire (SiNW) gate all-around (GAA) non-volatile memory with channel diameter down to 20nm. The junction-less devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application.
Keywords :
NAND circuits; elemental semiconductors; flash memories; nanowires; silicon; 3D multilevel NAND memory array; GAA; Si; SiNW; junction-less stackable SONOS memory; multilevel stacked ultra high density memory application; vertical Si-nanowire gate-all-around nonvolatile memory; Computer architecture; Doping; Junctions; Logic gates; SONOS devices; Tunneling; Wires;
Conference_Titel :
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4577-0225-9
Electronic_ISBN :
978-1-4577-0224-2
DOI :
10.1109/IMW.2011.5873187
