A 1.8 V 2.5 GHz PLL using 0.18 /spl mu/m SOI/CMOS technology

Summary form only given. This paper shows a 2.5 GHz PLL circuit for high-speed communication devices using a 0.18 /spl mu/m SOI/CMOS technology. The technology uses a shallow trench structure to effectively isolate active devices on a thin film SOI substrate. We employed floating-body SOI/CMOS in this chip. We applied a ring oscillator for the voltage controlled-oscillator (VCO). The well-known issues of SOI do not affect the circuit stability and noise performance of our PLL circuit for several reasons. Firstly, as the frequency range required for the VCO is comparatively narrow, the floating-body configuration would have little effect on circuit operation (Ueda et al., 1996). Secondly, thermal equilibrium on the ring oscillator can be achieved within a few microseconds (Tenbroek et al., 1998). Then the self-heating issue would be insignificant for the lock-in process of the PLL. Besides this, the buried oxide of SOI and shallow trench isolation reduces the crosstalk noise from the large digital logic block which is the most potentially serious problem for system-level integration of sensitive circuits and large logic blocks.