DocumentCode
3517975
Title
25nm 64Gb 130mm² 3bpc NAND Flash Memory
Author
Goldman, M. ; Pangal, K. ; Naso, G. ; Goda, A.
fYear
2011
fDate
22-25 May 2011
Firstpage
1
Lastpage
4
Abstract
25nm NAND technology-based 64Gb 3bpc NAND Flash memory with die size of 130mm2 (6.15GB/cm2) is presented. The design including the array architecture is optimized for 25nm process technology while achieving world class performance of 100μs tRD, 2300μs tPROG for write throughput of 6.8MB/s with reliability meeting business requirements.
Keywords
NAND circuits; flash memories; NAND flash memory; array architecture; reliability meeting business requirement; size 25 nm; Arrays; Couplings; Flash memory; Programming; Reliability; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4577-0225-9
Electronic_ISBN
978-1-4577-0224-2
Type
conf
DOI
10.1109/IMW.2011.5873197
Filename
5873197
Link To Document