Title :
Fabrication and optimization of wafer level SAW filter package using laser via drilling
Author :
Park, Seung Wook ; Hong, Ju Pyo ; Kim, Tae Hoon ; Yang, Si Joong ; Ha, Job ; Kim, Tae Ho ; Park, Sang Wook ; Kweon, Young Do ; Yi, Sung
Author_Institution :
Corp. R&D Inst., Samsung Electro-Mech. Co., Ltd., Suwon
Abstract :
Wafer level surface acoustic wave (SAW) filter package, 0.8times0.6 mm2, is drilled by laser via process. Via formation for interconnection is based on smaller package manufacture. LT (LiTaO3) which is base material of SAW filter is difficult to drill a small via by RIE (Reactive Ion Etching) because the RIE gets a very small etch rate and has wafer broken issue by thermal heating. So, our previous review is focused on the sand blasting process for via formation. However, there is limitation on via size and via depth and makes a leakage path at interface of Cu and via side wall by roughness and micro crack after electroplating. So, study on the laser via technology for meeting a design rule requests below 30 um via hole size and over 110 um depth. That gives a good solution of via formation for our package. However, the laser via makes the secondary issues such as debris and via shape, which disturb the electroplating of via inside. Overcoming these troubles and removing debris of via inside by new cleaning method are applied to general etching steps. Finally, we make a 0.8times0.6 mm2 SAW filter using laser via with etching steps compared with it using normal laser process. The result of electrical performance and laser process for wafer level SAW filter package is also discussed.
Keywords :
electroplating; interconnections; laser beam machining; lithium compounds; sputter etching; surface acoustic wave filters; LiTaO3; electroplating; laser via drilling; reactive ion etching; surface acoustic wave; thermal heating; wafer level SAW filter package; Acoustic waves; Drilling; Etching; Manufacturing; Optical device fabrication; Packaging; SAW filters; Surface acoustic waves; Surface emitting lasers; Wafer scale integration;
Conference_Titel :
Electronics System-Integration Technology Conference, 2008. ESTC 2008. 2nd
Conference_Location :
Greenwich
Print_ISBN :
978-1-4244-2813-7
Electronic_ISBN :
978-1-4244-2814-4
DOI :
10.1109/ESTC.2008.4684537