The off leakage in SOI-MOS transistors and the impact on the standby current of ULSI´s

Author

Adan, A.O. ; Higashi, K. ; Nimi, K. ; Ashida, T.

Author_Institution

IC Group, Sharp Corp., Nara, Japan

fYear

1999

fDate

4-7 Oct. 1999

Firstpage

34

Lastpage

35

Abstract

Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I/sub doff/<10 pA//spl mu/m, which should be compared with I/sub doff//spl sim/1 nA//spl mu/m in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the IC´s standby current for quantitative modeling. The model parameter extraction techniques are also described.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit modelling; leakage currents; low-power electronics; semiconductor device models; silicon-on-insulator; IC standby current; MOSFET off-current; SOI MOSFETs; SOI-CMOS low-voltage battery-powered device applications; SOI-MOS transistors; Si-SiO/sub 2/; ULSI; high-speed microprocessors; model parameter extraction techniques; off-current mechanism; off-leakage; off-state leakage current; portable electronic equipment; quantitative modeling; standby current; standby power dissipation specification; threshold voltage; Bismuth; Circuit testing; Current measurement; Diodes; Impact ionization; Leakage current; MOSFET circuits; Temperature; Threshold voltage; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1999. Proceedings. 1999 IEEE International

Conference_Location

Rohnert Park, CA, USA

ISSN

1078-621X

Print_ISBN

0-7803-5456-7

Type

conf

DOI

10.1109/SOI.1999.819845

Filename

819845