Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits

Circuit design using partially depleted (PD) SOI FETs must take into account a variable gate delay which is dependent on the switching history of the circuits (Gautier et al, 1997; Houston and Unnikrishnan, 1998). In order to fully exploit the advantages of SOI, it is important to understand and analyze such ´history effects´ and consider them for an optimized design strategy. In this paper, we describe a methodology suitable to analyze PD SOI CMOS circuits, including a new algorithm for dynamic equilibrium computations, a task that is not practicable with standard circuit simulators because of the very slow evolution of the body potential (time constants up to ms (Assaderaghi et al., 1996)). Simulation results for a 0.2 /spl mu/m technology are given, showing the importance of design and application parameters with regard to the history effect.