Study of Pass-Gate Voltage (VPASS) Interference in Sub-30nm Charge-Trapping (CT) NAND Flash Devices

For the first time the WL-WL pass-gate voltage (VPASS) interference for charge-trapping (CT) NAND Flash devices is studied experimentally. Using a 38nm half-pitch BE-SONOS NAND Flash device we find the threshold voltage decreases significantly with increasing VPASS during reading, contrary to the common believe that CT NAND devices are immune to the interference. We clarify that this extraordinary effect becomes significant for the scaled CT NAND Flash, where a lightly doped junction or junction-free device allows the fringing field caused by VPASS to penetrate into the selected cell and affects the inversion electron density. A small S/D junction recess or a non-cut ONO WL profile is suggested to minimize such effect. Moreover, we also find that the programming speed also decreases when a smaller VPASS PGM is applied. Based on our findings we suggest to use low-K spacer material between WL-WL in order to have better short-channel effect, lower interference and larger memory window for further scaling to sub-20 nm node.