DocumentCode
3518298
Title
Endurance Prediction of Scaled NAND Flash Memory Based on Spatial Mapping of Erase Tunneling Current
Author
Fayrushin, Albert ; Lee, ChangHyun ; Park, Youngwoo ; Choi, Jungdal ; Choi, Jeonghyuk ; Chung, Chilhee
Author_Institution
Flash Lab., Samsung Electron. Co. Ltd., Hwasung, South Korea
fYear
2011
fDate
22-25 May 2011
Firstpage
1
Lastpage
4
Abstract
In this work, we present novel endurance prediction technique for scaled NAND Flash memory with arbitrary size and shape. Predicted endurance curve is obtained by simulation of several program/erase (PGM/ERS) cycle steps with subsequent determination of midgap voltage. Each step of simulated PGM/ERS cycles corresponds to specific distribution of trapped charge concentration in tunnel oxide. Distribution function of the trapped charge is found through mapping of ERS tunneling current. Absolute value of the trapped charge is obtained via calibration of the reference device with known endurance curve (42 nm node). Using proposed method, endurance of 27 nm-node device has been extracted and verified.
Keywords
NAND circuits; flash memories; tunnelling; PGM-ERS cycle; erase tunneling current; program-erase cycle; scaled NAND flash memory; spatial mapping; trapped charge concentration distribution; tunnel oxide; Calibration; Charge carrier processes; Degradation; Electric fields; Flash memory; Silicon; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4577-0225-9
Electronic_ISBN
978-1-4577-0224-2
Type
conf
DOI
10.1109/IMW.2011.5873215
Filename
5873215
Link To Document