Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance

In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, R_d and R_s from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency f_T, until the on-current I_on becomes limited by increasing series resistances and f_T therefore reduces. The results indicate a thickness of 40 nm FILOX for maximum f_T. We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation.