DocumentCode
3518693
Title
The Operation Algorithm for Improving the Reliability of TLC (Triple Level Cell) NAND Flash Characteristics
Author
Lee, Dong Wook ; Cho, Sunghoon ; Kang, Byung Woo ; Park, Sukkwang ; Park, Byoungjun ; Cho, Myoung Kwan ; Ahn, Kun-Ok ; Yang, Ye Seok ; Park, Sung Wook
Author_Institution
Flash Device Eng., Flash Dev. Div., Hynix Semicond. Inc., Cheongju, South Korea
fYear
2011
fDate
22-25 May 2011
Firstpage
1
Lastpage
2
Abstract
As the NAND flash market demand for larger capacity with low cost increases, the feature-size scaling and multi-level per bit have been developed. In this paper, we present the newly adopted operation algorithms and their results such as intelligent ISPE(Incremental Step Pulse Erase), various biasing in grouped W/Ls and VNR(Virtual Negative Read) in TLC(Triple Level Cell) NAND flash.
Keywords
NAND circuits; flash memories; semiconductor device reliability; TLC NAND flash memory characteristics; VNR; incremental step pulse erase; intelligent ISPE; reliability improvement; triple level cell; virtual negative read; Flash memory; Interference; Optimization; Reliability; Silicon; Solid state circuits; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4577-0225-9
Electronic_ISBN
978-1-4577-0224-2
Type
conf
DOI
10.1109/IMW.2011.5873234
Filename
5873234
Link To Document