DocumentCode :
3518745
Title :
Observation and Effective Suppression of Dielectric Relaxation in Charge-Trap NAND Flash Memory
Author :
Sim, Jae Sung ; Choi, Jungdal ; Kang, Changseok ; Park, Youngwoo ; Park, Jintaek ; Choi, Jeong-Hyuk ; Chung, Chilhee
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwasung, South Korea
fYear :
2011
fDate :
22-25 May 2011
Firstpage :
1
Lastpage :
2
Abstract :
We measured instant VΛ change coming from the relaxation effect in high-k dielectric layer in CTF. A counter-pulse scheme was proposed to solve the issue in CTF memory, by inserting short positive gate pulse between erase execution pulse and verify read step, whose validity was confirmed in our NAND test vehicle main cell array.
Keywords :
NAND circuits; counting circuits; dielectric relaxation; flash memories; CTF memory; NAND test vehicle main cell array; charge-trap NAND flash memory; counter-pulse scheme; dielectric relaxation effective suppression; high-k dielectric layer; Dielectric measurements; Dielectrics; Flash memory; High K dielectric materials; Logic gates; Semiconductor device measurement; Transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4577-0225-9
Electronic_ISBN :
978-1-4577-0224-2
Type :
conf
DOI :
10.1109/IMW.2011.5873237
Filename :
5873237
Link To Document :
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