Thin wafer handling and processing-results achieved and upcoming tasks in the field of 3D and TSV

As microelectronic applications and technologies are getting more demanding, it is being demonstrated that the 3^rd (vertical) dimension on wafer-processing technology is enabling applications and products with higher performance. Approaching the 3^rd dimension in wafers is actually considered and realized through emerging TSV (through silicon via) technology and thinned wafers at the same time. Thin (<100 ¿m) silicon wafers which are commonly used for TSV formation exhibit increased instability and fragility. The lack of mechanical stability and the increased fragility present a major challenge to maintain high yield levels in volume manufacturing environments. The most accepted handling solution for UltraThin^® wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via (TSV) formation, etc. The product wafers can be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. Additional stacking of ultra thin wafers or bonding chips to thin wafers are new requirements to be considered.