Inverse modeling of sub-100nm MOSFET with PDE-constrained optimization

The inverse modeling of MOSFET aims to extract the process and device parameters of a CMOS technology from electrical test data, such as the I-V curves. In this work, an inverse modeling approach that efficiently calculates the partial derivatives is outlined, and extraction result on a 65 nm CMOS technology is presented. In particular, instead of fitting to I-V curves of one transistor, this work attempts to fit to all device sizes, from the shortest gate length to the long-channel ones.