Very linear ramp-generators for high resolution ADC BIST and calibration

Author

Wang, Jing ; Sanchez-Sinencio, Edgar ; Maloberti, Franco

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

2

fYear

2000

fDate

2000

Firstpage

908

Abstract

Two very linear ramp-generator designs are presented. The circuits are to be used in high-resolution ADC built-in-self-test (BIST) and on-chip calibration. The first design is used to charge a capacitor by a small current, which is linear enough to test 14-bit ADCs. The second design is in a relaxation oscillator architecture. It is linear enough to test up to 12-bit ADCs. The two designs have been fabricated in CMOS 2 μm and 1.2 μm processes separately

Keywords

CMOS integrated circuits; analogue-digital conversion; built-in self test; capacitors; circuit simulation; integrated circuit design; integrated circuit testing; linear network synthesis; ramp generators; relaxation oscillators; 1.2 micron; 12 bit; 14 bit; 2 micron; ADC built-in-self-test; ADC on-chip calibration; ADC test; CMOS processes; capacitor charging current; high resolution ADC BIST; high resolution ADC calibration; linear ramp-generator designs; relaxation oscillator architecture; very linear ramp-generators; Built-in self-test; CMOS technology; Calibration; Capacitors; Circuit testing; Digital signal processing; Digital signal processing chips; Impedance; Pipelines; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.952901

Filename

952901