• DocumentCode
    3520675
  • Title

    Thin die stacking by low temperature In/ Au IMC based bonding method

  • Author

    Ong, Siong Chiew ; Choi, Won Kyoung ; Premachandran, C.S. ; Liao, Ebin ; Xie, Ling

  • Author_Institution
    Inst. of Microelectron., A*STAR, Singapore, Singapore
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    464
  • Lastpage
    468
  • Abstract
    Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200°C forming robust intermetallics (IMC) joints with high re-melting temperature (>300°C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as such chips are temporary bonded onto wafer before the final bonding. The chips are bonded onto the wafer by two sequential bonding condition; temporary followed by a final bonding, which is 200/90°C (chip/wafer) for 20 sec and 180/180°C for 5 mins. The IMC joints are evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. These IMC joint showed a tensile strength of 120~330 N (23.5~38.8 MPa). Based on this study, the 3 stacked dice with 8 × 8 mm2 dies with ~1700 I/Os of 80 um solder bumps were fabricated in a chip to wafer stacking method. It showed uniform bonding all over the die in each layer with relatively good tensile strength achieved. Furthermore, it also underwent 3 times reflow test at 260°C. The IMC joint was examined after going through the reflows test and the bonded samples exhibited neither de-lamination nor any changes in the microstructure.
  • Keywords
    gold; indium alloys; semiconductor device packaging; solders; stacking; tensile strength; wafer bonding; chip to wafer stacking; chips to wafer bonding; compositional observations; low temperature bonding; microstructure; remelting temperature; robust intermetallics; scanning electron microscope; sequential bonding condition; solder bumps; solder system; tensile strength; thin die stacking; time 20 s; time 5 min; transmittance electron microscope; Gold; Intermetallic; Microstructure; Robustness; Scanning electron microscopy; Stacking; Temperature; Testing; Transmission electron microscopy; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-5099-2
  • Electronic_ISBN
    978-1-4244-5100-5
  • Type

    conf

  • DOI
    10.1109/EPTC.2009.5416503
  • Filename
    5416503