DocumentCode
3520743
Title
Bottom-up filling of Through Silicon Via (TSV) with Parylene as sidewall protection layer
Author
Miao, Min ; Zhu, Yunhui ; Ji, Ming ; Ma, Shenglin ; Sun, Xin ; Jin, Yufeng
fYear
2009
fDate
9-11 Dec. 2009
Firstpage
442
Lastpage
446
Abstract
In this paper, we present our recent advances in streamlining via-last TSV process flow. Parylene deposition, which is of excellent conformability to the substrate landscape, was introduced into TSV blind via filling process to realize uniform sidewall protection. Simulation was made to analyze the impacts of parylene sidewall on the electric field distribution inside a blind via with high aspect ratios during electroplating, which indicates that a uniform plating current density distribution may be achieved with the help of the parylene sidewall, and thus a void-free filling can be guaranteed. Then in experimental microfabrication runs, with parylene sidewall protection, we achieved bottom-up filling of blind TSV of large ratio aspect at a higher rate. Besides, during our experiments, a ¿bottom-up plus non-bottom-up¿ filling methodology is proposed and the microfabrication trials demonstrate its potential capability of filling TSV blind via at a much higher rate.
Keywords
electric fields; electroplating; microfabrication; substrates; Si; bottom-up filling; electric field distribution; electroplating; microfabrication; parylene deposition; sidewall protection layer; substrate landscape; through silicon via; Computed tomography; Detectors; Electronics packaging; Filling; Inspection; Integrated circuit packaging; Protection; Silicon; Through-silicon vias; X-ray imaging;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
Conference_Location
Singapore
Print_ISBN
978-1-4244-5099-2
Electronic_ISBN
978-1-4244-5100-5
Type
conf
DOI
10.1109/EPTC.2009.5416507
Filename
5416507
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