Title :
Exploring MOL design options for a 20nm CMOS technology using TCAD
Author :
Scholze, Andreas ; Furkay, Stephen ; Kim, Seong-Dong ; Jain, Sameer
Author_Institution :
Semicond. R&D Center, IBM, Essex Junction, VT, USA
Abstract :
A mixed-mode simulation framework is presented to study the AC performance of a 20nm bulk CMOS technology with respect to various options for contact design at the middle-of-line design level. These simulations combine the predictive capabilities of a calibrated two-dimensional TCAD model for a MOSFET with three-dimensional simulations for the layout dependent parasitic capacitances to extract the characteristic parameters of a multi-stage ring-oscillator circuit, such as the ring delay, and the effective switching capacitance. Significant performance degradation is predicted comparing the simulation results for a conventional contact design versus a typical 20nm design considering raised source-drain and a contact bar.
Keywords :
CMOS integrated circuits; MOSFET; calibration; oscillators; technology CAD (electronics); AC performance; MOL design level; MOSFET; bulk CMOS technology; layout dependent parasitic capacitance; middle-of-line design level; mixed-mode simulation framework; multi-stage ring-oscillator circuit; ring delay; size 20 nm; switching capacitance; three-dimensional simulation; two-dimensional TCAD model; Capacitance; Delay; Integrated circuit modeling; Inverters; Logic gates; MOSFET circuits; Semiconductor device modeling;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on
Conference_Location :
Osaka
Print_ISBN :
978-1-61284-419-0
DOI :
10.1109/SISPAD.2011.6035059
