Title :
Improved design of C2PL 3-2 compressors with less transistor count
Author :
Wang, Chua- Chin ; Lee, Po-Ming ; Hunng, Chenn- Jung
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
In this work, improved designs of 3-2 C2PL-based compressors are presented which can be used to build a fast inner product processor. The features of our compressors include a short delay minimized by HSPICE optimization, less transistor count, and high fan-out
Keywords :
CMOS logic circuits; VLSI; adders; delays; digital arithmetic; logic design; C2PL 3-2 compressors; HSPICE optimization; delay minimization; fast inner product processor; high fan-out; transistor count reduction; CMOS logic circuits; Clocks; Compressors; Degradation; Logic design; Noise level; Propagation delay; Robustness; Silicon; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.858688
