Development of high speed board level bend tester for drop impact applications

Due to the widespread use of portable electronics, there is a significant increase in interest in exploring the impact reliability of electronic packaging during impact shock. Currently, the test standard used for board level drop testing is JESD 22-B111, which specifies the impact pulse (i.e. 1500 G at 0.5 ms) as a criterion for drop testing. However, this may not mimic the actual product testing. The board level cyclic bend test standard (JESD 22-B113) is subsequently developed and introduced to perform low frequency bending (1 to 3 Hz). However, cyclic bend at low frequency is not able to produce similar failure mode as drop testing because board frequency during drop impact is usually much higher. Thus in this study, a high speed bend test (>50 Hz) is developed to perform strain-controlled bend testing. The strain amplitude and frequency effects on BGA and WLCSP package solder joint life on various board sizes and component layout are studied and discussed. An increase in frequency was found to result in a significant reduction in time to failure, though a shift in failure mode (from bulk solder to inter-metallic failure) and reduction in cycles to failure were not observed. Results indicated that at higher strain amplitudes, cycles to fatigue life of package significantly decreased. This study has also shown a certain extent of correlation between drop test and high speed bend test.