Title :
Application of a statistical design methodology to low voltage analog MOS integrated circuits
Author :
Tarim, Tuna B. ; Ismail, Mohammed
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 μm process using MOS transistor Level-3 model parameters. The experimental results are included in the paper
Keywords :
MOS analogue integrated circuits; VLSI; integrated circuit design; integrated circuit yield; low-power electronics; statistical analysis; Level-3 model parameters; MOSIS; current division network; four-MOSFET structure; low voltage analog MOS ICs; statistical design methodology; transistor mismatch; yield enhancement; Circuit simulation; Design methodology; Fluctuations; Integrated circuit reliability; Integrated circuit yield; Logic; Low voltage; MOS integrated circuits; MOSFETs; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.858702
