Board level drop impact reliability analysis for compliant wafer level package through modeling approaches

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. In this paper, a new compliant Wafer Level Package technology is proposed which can accommodate the CTE mismatch between the chip and PCB substrate and consequently should be more reliable without the application of underfill. The purpose of this study is to explore the solder joint reliability of the new compliant WLP during drop impact and optimize the design of compliant lead. The input acceleration (Input-G) method is applied to simulate the exact drop test process subjected to JEDEC board level drop test conditions. Several types of compliant lead shape with different sizes are studied by comparing and analyzing the dynamic responses of CWLP solder joints under board level drop test, the copper trace reliability of these types CWLP are compared, further more, the optimal parameters of the compliant lead are confirmed by design of experiment (DOE). The board level drop test simulation illustrated the ability of the compliant Wafer Level Package to reduce the stress in the solder interconnects. It is observed that the highest stress appears in the copper trace, while copper trace can flex and effectively absorb the stress between the chip and the bump pad. This in turn will lead to an increase in the reliability of the assembly.