Title :
Vstyle: a coding style analyzer for synthesizable Verilog
Author_Institution :
Data General Corp., USA
Abstract :
The paper describes the implementation of Vstyle, a proprietary Verilog coding style checker implemented in yacc and c. The emphasis is not on any particular set of coding practices, but on how to craft a tool which validates that coding practices are being followed. As with any proprietary tool, the benefits must be weighed with the cost of development and support. The paper demonstrates a method of implementation which delivers the most basic style verification with a modest coding effort, and which can be extended over time to yield increasing benefit
Keywords :
formal verification; hardware description languages; software tools; system monitoring; Verilog coding style checker; Vstyle; coding practices; coding style analyzer; synthesizable Verilog; validation tool; Clocks; Computer industry; Costs; Degradation; Guidelines; Hardware design languages; Process design; Software standards; Standards organizations; Testing;
Conference_Titel :
Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-7431-8
DOI :
10.1109/IVC.1996.496018
