Full thermal parametric model for power WL-CSP design

A new type of full thermal parametric model for power wafer level chip scale package (WL-CSP) is developed in this paper, which includes parametric WL-CSP and its adaptive parametric JEDEC thermal test board. By employment of the parametric model, package geometry parameters and the trace layout for PCB can easily be changed to meet the requirement of design, so that the influence of all geometry parameters to thermal performance can be investigated fast for the whole series of WL-CSP packages. The entire thermal simulation, including meshing, loading/boundary condition, solving, and post processing, is automated with ANSYS^reg parametric design language (APDL) coding. This paper introduces the construction of the parametric model for WL-CSP design, and both JEDEC low effective thermal board and high effective thermal conductivity boards with and without thermal vias are included in the model. To study impact of solder ball number, die size, terminal pitch on thermal resistances or parameters, extensive modeling tasks are run and related results are systemically investigated. As verification, a WL-CSP with 6 balls is actually tested finally, and results show that it is a good match between actual measurement and simulation results.