DocumentCode :
3522440
Title :
Handling branches in TLS systems with Multi-Path Execution
Author :
Xekalakis, Polychronis ; Cintra, Marcelo
Author_Institution :
Intel Barcelona Res. Center, Intel Labs. Barcelona - UPC, Barcelona, Spain
fYear :
2010
fDate :
9-14 Jan. 2010
Firstpage :
1
Lastpage :
12
Abstract :
Thread-Level Speculation (TLS) has been proposed to facilitate the extraction of parallel threads from sequential applications. Most prior work on TLS has focused on architectural features directly related to supporting the main TLS operations. In this work we, instead, investigate how a common microarchitectural feature, namely branch prediction, interacts with TLS. We show that branch prediction for TLS is even more important than it is for sequential execution. Unfortunately, branch prediction for TLS systems is also inherently harder. Code partitioning and re-executions of squashed threads pollute the branch history making it harder for predictors to be accurate. We thus propose to augment the hardware, so as to accommodate Multi-Path Execution (MP) within the existing TLS protocol. Under the MP execution model, all paths following a number of hard-to-predict conditional branches are followed simultaneously. MP execution thus removes branches that would have been otherwise mispredicted, helping in this way the core to exploit more ILP. We show that, with only minimal hardware support, one can combine these two execution models into a unified one. Experimental results show that our combined execution model achieves speedups of up to 23.2%, with an average of 9.2%, over an existing state-of-the-art TLS system and speedups of up to 138 %, with an average of 28.2%, when compared with MP execution for a subset of the SPEC2000 Int benchmark suite.
Keywords :
multi-threading; parallel processing; SPEC2000 Int benchmark suite; branch prediction; code partitioning; hard-to-predict conditional branches; microarchitectural feature; multipath execution; parallel thread extraction; sequential applications; squashed threads reexecution; thread-level speculation; Hardware; History; Informatics; Microarchitecture; Moore´s Law; Pollution; Program processors; Programming profession; Protocols; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on
Conference_Location :
Bangalore
ISSN :
1530-0897
Print_ISBN :
978-1-4244-5658-1
Type :
conf
DOI :
10.1109/HPCA.2010.5416632
Filename :
5416632
Link To Document :
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