Novel pattern-based power estimation tool with accurate glitch modeling

In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is presented. With little addition in computational cost from the traditional event driven simulation the new technique employs better delay modeling of glitch peaks through the introduction of glitch coefficients and appropriate glitch filtering to achieve improvement in accuracy. The simulator is shown to reduce the estimation error by up to 50% from the traditional toggle-based technique, and has accuracy within 10% of SPICE. The simulator post-processes Verilog-XL output and the overall run-time is better than SPICE by more than an order of magnitude