Title :
A efficient placement and global routing algorithm for hierarchical FPGAs
Author :
Tang, Jing-Jou ; Wang, Ping-Tsung
Author_Institution :
Dept. of Electron. Eng., Southern Taiwan Univ. of Technol., Taiwan
Abstract :
In this paper an efficient placement and global routing algorithm for the hierarchical FPGAs (HFPGAs) is developed. This algorithm is based on a modified k-way min-cut technique which recursively partitions a cluster in k sub-clusters to facilitate the architecture of the HFPGAs. Through this algorithm, both the placement and global routing can be done simultaneously. The results of on a set of MCNC benchmark circuits show that the proposed algorithm is very efficient
Keywords :
field programmable gate arrays; logic CAD; logic partitioning; network routing; global routing algorithm; hierarchical FPGA; modified k-way min-cut technique; placement algorithm; recursive cluster partitioning; Algorithm design and analysis; Circuit synthesis; Clustering algorithms; Field programmable gate arrays; Hardware; Logic; Partitioning algorithms; Resource management; Routing; Switches;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.858855
