Title :
Integrated 64-state parallel analog Viterbi decoder
Author :
He, Kai ; Cauwenberghs, Gert
Author_Institution :
Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
Abstract :
We present a mixed-signal VLSI architecture for state-parallel analog Viterbi decoding, including an analog Add-Compare-Select (ACS) module and a digital survivor path memory (PM) module. A single-chip 64-state analog Viterbi decoder for K=7 convolutional code has been implemented in 3.3 V 0.5 μm CMOS technology. The chip measures 5.05×2.54 mm2, and achieves a decoding speed of 40 Mb/s (20 MHz clock) at 50 mW power consumption as verified by post-layout transistor-level simulation. In addition, a behavioral model accounting for inaccuracies in the analog implementation is developed to simulate the bit error rate (BER) vs. signal-to-noise (SNR) performance, confirming superior error correction (coding gain) of the mixed-signal design over hard-decision and 3-bit soft-decision digital implementations
Keywords :
CMOS integrated circuits; VLSI; Viterbi decoding; circuit simulation; convolutional codes; error correction; mixed analogue-digital integrated circuits; 0.5 micron; 20 MHz; 3.3 V; 40 Mbit/s; 50 mW; CMOS technology; analog add-compare-select module; behavioral model; bit error rate; coding gain; convolutional code; decoding speed; digital survivor path memory module; error correction; mixed-signal VLSI architecture; post-layout transistor-level simulation; power consumption; signal-to-noise ratio; state-parallel analog Viterbi decoder; Bit error rate; CMOS technology; Clocks; Convolutional codes; Decoding; Power measurement; Semiconductor device measurement; Velocity measurement; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.858863
