Integrated 64-state parallel analog Viterbi decoder

We present a mixed-signal VLSI architecture for state-parallel analog Viterbi decoding, including an analog Add-Compare-Select (ACS) module and a digital survivor path memory (PM) module. A single-chip 64-state analog Viterbi decoder for K=7 convolutional code has been implemented in 3.3 V 0.5 μm CMOS technology. The chip measures 5.05×2.54 mm², and achieves a decoding speed of 40 Mb/s (20 MHz clock) at 50 mW power consumption as verified by post-layout transistor-level simulation. In addition, a behavioral model accounting for inaccuracies in the analog implementation is developed to simulate the bit error rate (BER) vs. signal-to-noise (SNR) performance, confirming superior error correction (coding gain) of the mixed-signal design over hard-decision and 3-bit soft-decision digital implementations